Conventionally, cellular phone devices, PDA (Personal Digital Assistant) terminals, or other many electronic devices include a printed circuit board on which a lot of electronic components are mounted in a limited space. With smaller geometries and higher performance of electronic devices, a printed circuit board (especially a multilayer printed circuit board) capable of mounting semiconductor devices such as LSIs at a high density has come to be used. In such a multilayer printed circuit board, an interlayer interconnecting technology capable of establishing electrical connection between wiring patterns of a plurality of layers formed with fine wiring pitches, with high connection reliability, is important. In a via structure used for interlayer connection in the multilayer printed circuit board, in particular, various proposals for achieving smaller geometries and higher reliability have been made.
However, in recent years, ergonomic design targeted for improving outward appearance beauty, operability, and transportability is demanded for the electronic devices. Accordingly, there is an increasing demand for improving a degree of freedom with respect to a shape of the printed circuit board, especially for a curved printed circuit board.
As methods of establishing electrical connection between wiring patterns of a plurality of layers on the conventional printed circuit board, a method (A) of forming a conformal via (hollow via) by applying copper plating along a lower hole for the conformal via and a method (B) of forming a filled via (solid via) by filling an electrically conductive material into a lower hole for the filled via, and the like may be pointed out.
First, as an example of forming the conformal via, there is a method (Related Art 1) disclosed in Patent Document 1, for example. This is a method of forming a via 105 in a base 103 formed of an insulating layer 104 made of a synthetic resin material, as shown in FIG. 26. On both surfaces of the base 103, wiring layers 101 and 102 are formed, respectively. One end of the via 105 opens to one surface of the insulating layer 104 and the other end of the via 105 is closed by the wiring layer 102 on the other surface of the insulating layer 104. By a first plating process, an inside of the via 105, the wiring layer 101 on the other surface exposed within the via 105, and the wiring layer 102 on the one surface of the insulating layer are covered with a plating layer 106. Then, by applying a second plating process, a second plating layer 107 is laminated on the first plating layer 106 within the via 105. Through these plating layers, the wiring layers on both of the surfaces of the insulating layer 104 are electrically connected.
Next, as an example of forming the filled via, there is a method (Related Art 2-1) disclosed in Patent Document 2, for example. In this method, an epoxy resin layer 203 is laminated on a double-sided copper clad with copper circuits 201 provided on a surface thereof, as shown in FIG. 27. Then, via holes 204 are formed by laser processing. A process of activating surfaces of the copper circuits 201 is performed, and an electroless copper plating process is applied, thereby forming electroless copper plating layers 206 on activated regions 205 on the surfaces of the copper circuits 201, respectively. A Pd catalyst 207 is deposited on exposed surfaces of the copper circuits 201 and the epoxy resin layer 203. Then, by applying the electroless plating process, a plated seed layer 208 is formed over the exposed surfaces of the copper circuits 201 and the epoxy resin layer 203. Then, by applying an electrolytic plating process, an electrolytic copper plating layer 209 is formed over the plated seed layer 208, thereby burying the via holes.
Patent Document 2 further presents a build-up multilayer wiring board structure that uses a common filled via (Related Art 2-2). In this method, as shown in FIG. 28, on a double-sided copper clad 225 with copper circuits 221 provided on both surfaces thereof and with a through conductor 222, a power supply layer 223, and a GND layer 224 provided inside thereof, copper wiring layers 227 that form electronic circuit patterns are provided in multiple layers through inter-layer insulating films formed of epoxy resin layers 226. The copper wiring layers 227 of the multiple layers are interconnected by vias 228 of which via holes are buried.
As other method of forming the filled via, there is a method (Related Art 3) disclosed in Patent Document 3, for example. In this method, as shown in FIG. 29, using a step of providing through holes 303 in a compressible porous base material 302 provided with releasing (releasable) films 301, filling a conductive paste 304 into each of the through holes 303, permeating a binder component of the paste into the porous base material 302, thereby increasing a composition ratio of a conductive material to a binder of the paste, and a step of adhering metal foils 305 to surfaces of the base material with the releasing films 301 separated and removed therefrom, for heating and pressurization, and compressing the laminated base material, the conductive material is densified, thereby achieving electrical connection between the metal foils.    Patent Document 1: JP Patent Kokai Publication No. JP-P-2002-26515A (paragraphs [0042] to [0061], FIGS. 1 to 9)    Patent Document 2: JP Patent Publication No. 3596476 (paragraphs [0005], [0058] to [0068], FIGS. 3, 4, and 8)    Patent Document 3: JP Patent Publication No. 2601128 (paragraphs [0018] to [0019], FIG. 1)